1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and more particularly, to a method of manufacturing semiconductor devices in each of which a circuit pattern having a size larger than the field size that can be obtained by one exposure operation of a reduction projection exposure device is formed on a semiconductor substrate.
2. Related Barkground Art
In a conventional semiconductor device manufacturing method, semiconductor devices having a large chip size are formed on semiconductor substrates utilizing the equal size projection technique, which is accomplished by the use of, for example, a reflection type projection exposure device. A reduction projection exposure device has not been used.
In conventional semiconductor devices, a single IC chip generally has a single major function, e.g., a microcomputer or memory function, because provision of a plurality of sufficient functions in a single IC chip increases the chip size greatly. Provision of an IC chip having a pattern containing a plurality of functions requires the reduction projection exposure technique which is capable of projecting an area larger than that which can be projected by one operation of the reduction projection exposure device. It is therefore impossible to form a circuit pattern in which a plurality of sufficient functions are formed in an area which can be projected by one exposure process step.
In recent years, the chip size has been increased and the pattern size has become fine. Regarding this, the use of a reflection type projection exposure device arouses various problems. Such problems will be described in detail with reference to FIG. 1 which shows an example of a reflection type projection exposure device.
The reflection type projection exposure device has an optical system which includes a combination of concave mirror 11 and a convex mirror 12 and which employs an arcuate slit-shaped illumination 13. In this device, an image of the pattern on the mask 14 is transferred on the entire surface of the wafer 15 at a projection ratio of 1:1 by synchronously moving a mask 14 and a wafer 15 in the direction indicated by arrows A in FIG. 1. When it is desired to manufacture semiconductor devices having a large chip size, the mask pattern can be transferred onto the wafer 15 using a mask having a pattern whose size is the same as the chip size. This technique achieves resolution of about 2 .mu.m. It is therefore very difficult to form a fine pattern having a design rule of, for example, 0.5 to 1.0 .mu.m and thereby increase the integration density. Since alignment is conducted using alignment marks formed at the right and left sides of a wafer, alignment accuracy is limited to 3.sigma.=1.5 .mu.m. With the reflection projection exposure device of the above-described type, it is therefore impossible to form fine patterns having a design rule of submicron.
In other words, the reflection type projection exposure device, which is used to form IC chips having a size which is the same as the mask size, cannot cope with the increasing demands for forming finer patterns in terms of the resolution and alignment accuracy.
Furthermore, when the above-described type of exposure device is used, distortion of the hardware deteriorates the degree of orthogonalization of a formed pattern and automatic alignment accuracy between the adjoining manufacturing processes is limited to 3.sigma..congruent.1.5 .mu.m. These preclude the exposure device from coping with formation of patterns having a design rule of submicron.
That is, when semiconductor devices having a large chip size are manufactured, the use of the reflection type projection exposure device has the following drawbacks.
(1) Since the resolution achieved by the exposure device is 2.5 to 3 .mu.m, it is impossible to form fine patterns having a design rule of, for example, 0.5 to 1.0 .mu.m and thereby increase the integration density.
(2) Distortion of the hardware deteriorates the degree of orthogonalization of the pattern.
(3) Since automatic alignment accuracy between the processes is 3.sigma..congruent.1.5 .mu.m, it is impossible to cope with demands for forming fine patterns having a design rule of submicron.
To improve the resolution or alignment accuracy, a reduction projection exposure device may be used. As shown in FIG. 2 which illustrates an example of a reduction projection exposure device, in the reduction projection exposure device, the image of a pattern formed on a reticle is demagnified at a demagnification ratio inherent in a reduction projection lens 23 and projected onto a wafer 27. After the exposure of one shot, the wafer is moved or stepped on an XY stage 28, and the process is repeated. This step-and-repeat projection exposure technique achieves approximately 1.0 .mu.m resolution. Since alignment is conducted after exposure of each shot, alignment accuracy of 3.sigma..congruent.0.2 is achieved.
When semiconductor devices having a large chip size are formed using the reduction projection exposure device, it is considered to use a lens not having a demagnification ratio of 5:1 or 10:1 but a demagnification ratio of 2.5:1. In that case, the exposure area (field size) is practically .o slashed.40 mm. This is because it is possible to increase the mask size but it is impossible to provide an optical system of the exposure device which is capable of projecting that mask image on a large exposure area without causing distortion or irregularities. It is therefore impossible to manufacture semiconductor devices having a chip size of 50 mm or more and having fine patterns by utilizing the conventional techniques.